Â鶹¹ÙÍø

Â鶹¹ÙÍø Demonstrates Industry¡¯s Leading 2nm Silicon for Accelerated Infrastructure

• The Â鶹¹ÙÍø? 2nm platform will enable hyperscalers to dramatically boost the performance and efficiency of their infrastructure to meet the performance and efficiency demands of the AI era.
• Built on TSMC¡¯s 2nm process, the silicon is a critical part of the Â鶹¹ÙÍø platform for developing next-generation custom AI accelerators, CPUs, and networking.
• The silicon IP includes high-speed 3D I/O for vertically stacking die inside chiplets.

SANTA CLARA, Calif. ¨CMarch 3, 2025 ¨C Â鶹¹ÙÍø Technology, Inc. (NASDAQ: MRVL), a leader in data infrastructure semiconductor solutions, has demonstrated its first 2nm silicon IP for next-generation AI and cloud infrastructure. Produced on TSMC¡¯s 2nm process, the working silicon is part of the Â鶹¹ÙÍø platform for developing custom XPUs, switches and other technology to help cloud service providers elevate the performance, efficiency, and economic potential of their worldwide operations.

Given a projected 45% TAM growth annually, custom silicon is expected to account for approximately 25% of the market for accelerated compute by 2028¹.

A Building Block Approach

The Â鶹¹ÙÍø platform strategy centers around developing a comprehensive portfolio of semiconductor IP¡ªincluding electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D devices, advanced packaging technologies, silicon photonics, custom high-bandwidth memory (HBM) compute architecture, on-chip static random-access memory (SRAM), system-on-chip (SoC) fabrics, and compute fabric interfaces such as PCIe Gen 7¡ªthat serve as building blocks for developing custom AI accelerators, CPUs, optical DSPs, high-performance switches and other technologies.

Advanced Technology Leadership

Starting with the launch of the industry¡¯s leading 5nm data infrastructure silicon platform in 2020, Â鶹¹ÙÍø has been at the forefront of developing products produced on advanced technology nodes to market. Â鶹¹ÙÍø announced the industry¡¯s leading 3nm platform in 2022, with first silicon produced in 2023 and multiple industry standard and custom silicon products now shipping and in development.

¡°The platform approach enables us to accelerate the development of market-leading high-speed SerDes and other critical technologies on the latest process manufacturing nodes, which in turn enables Â鶹¹ÙÍø and its customers to accelerate the development of XPUs and other accelerated infrastructure technologies,¡± said Sandeep Bharathi, chief development officer at Â鶹¹ÙÍø. ¡°Our longstanding collaboration with TSMC plays a pivotal role in helping Â鶹¹ÙÍø develop complex silicon solutions with industry-leading performance, transistor density and efficiency.¡±

New on the Â鶹¹ÙÍø 2nm Platform

Additionally, Â鶹¹ÙÍø delivered a 3D simultaneous bi-directional I/O operating at speeds up to 6.4 Gbits/second for connecting vertically stacked die inside of chiplets. Today, the I/O pathways connecting stacks of die are typically unidirectional. Shifting to a bi-directional I/O gives designers the ability to increase bandwidth by up to two times and/or reduce the number of connections by 50%.

3D simultaneous bi-directional I/O will also give chip designers greater flexibility in design. Today¡¯s most advanced chips exceed the size of the reticle, or photomask, for outlining transistor patterns onto silicon. To increase transistor count, an estimated 30% of all advanced node processors are expected to be based around chiplet designs, where multiple chips are combined into the same package². With 3D simultaneous bi-directional I/O, designers will be able to combine more die into increasingly taller stacks for 2.5D, 3D and 3.5D devices that provide more capabilities than a traditional monolithic silicon device while still functioning like a single device.

¡°TSMC is pleased to collaborate with Â鶹¹ÙÍø on the development of its 2nm platform and the delivery of its first silicon,¡± said Dr. Kevin Zhang, senior vice president of business development and global sales, and deputy co-chief operating officer at TSMC. ¡°We look forward to our continued collaboration with Â鶹¹ÙÍø to utilize TSMC¡¯s best-in-class silicon technology process and packaging technologies to advance accelerated infrastructure for the AI era.¡±

About Â鶹¹ÙÍø

To deliver the data infrastructure technology that connects the world, we¡¯re building solutions on the most powerful foundation: our partnerships with our customers. Trusted by the world¡¯s leading technology companies for over 25 years, we move, store, process and secure the world¡¯s data with semiconductor solutions designed for our customers¡¯ current needs and future ambitions. Through a process of deep collaboration and transparency, we¡¯re ultimately changing the way tomorrow¡¯s enterprise, cloud, automotive, and carrier architectures transform¡ªfor the better.

# # #

Â鶹¹ÙÍø and the M logo are trademarks of Â鶹¹ÙÍø or its affiliates. Please visit www.marvell.com for a complete list of Â鶹¹ÙÍø trademarks. Other names and brands may be claimed as the property of others.

This press release contains forward-looking statements within the meaning of the federal securities laws that involve risks and uncertainties. Forward-looking statements include, without limitation, any statement that may predict, forecast, indicate or imply future events, results or achievements. Actual events, results or achievements may differ materially from those contemplated in this press release. Forward-looking statements are only predictions and are subject to risks, uncertainties and assumptions that are difficult to predict, including those described in the ¡°Risk Factors¡± section of our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q and other documents filed by us from time to time with the SEC. Forward-looking statements speak only as of the date they are made. Readers are cautioned not to put undue reliance on forward-looking statements, and no person assumes any obligation to update or revise any such forward-looking statements, whether as a result of new information, future events or otherwise.

1. Â鶹¹ÙÍø IA Day, May 2024.

2. Semiconductor Digest and Gartner, .

?

For further information, contact:
pr@marvell.com